The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to a carrier head for a chemical mechanical polishing system.
Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semiconductive or insulative layers. After each layer is deposited, the layer is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e., the exposed surface of the substrate, becomes increasingly non-planar. This non-planar surface presents problems in the photolithographic steps of the integrated circuit fabrication process. Therefore, there is a need to periodically planarize the substrate surface.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing pad. The polishing pad may be either a "standard" pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles, if a standard pad is used, is supplied to the surface of the polishing pad. The interaction of the polishing pad and the abrasive particles with the reactive sites results in polishing.
Typically, the carrier head includes a retaining ring. The retaining ring is positioned around the substrate to hold it beneath the carrier head. The retaining ring may be directly attached to the carrier head, or it may be connected to the carrier head by a flexible connector, such as a flexible membrane or bellows.
An effective CMP process should provide a high polishing rate yet generate a substrate surface that is finished (lacks small-scale roughness) and flat (lacks large-scale topography). The polishing rate, finish and flatness are determined by the pad and slurry combination, the relative speed between the substrate and pad, and the force pressing the substrate against the pad. Because inadequate flatness and finish can create defective substrates, the selection of a polishing pad and slurry combination is usually dictated by the required finish and flatness. Given these constraints, the polishing rate sets the maximum throughput of the polishing apparatus.
Among other factors, the polishing rate depends upon the force with which the substrate is pressed against the pad. Specifically, the greater this force, the higher the polishing rate. If force pressure is applied to one region of the substrate than to another, then the high pressure regions will be polished faster than the low pressure regions. Therefore, this will result in non-uniform polishing of the substrate.
One problem is that the edge of the substrate is often polished at a different rate (usually faster, but occasionally slower) than the center of the substrate. This problem, termed the "edge effect", may occur even if the load is uniformly applied to the substrate. The edge effect typically occurs in the perimeter portion, e.g., the outermost five to ten millimeters, of the substrate. The edge effect reduces the overall flatness of the substrate, makes the perimeter portion of the substrate unsuitable for integrated circuits, and decreases substrate yield.
Therefore, there is a need for a CMP apparatus that optimizes polishing throughput while providing the desired flatness and finish. Specifically, the CMP apparatus should have a carrier head which provides substantially uniform polishing of a substrate.